The present invention relates to operational amplifiers and in particular to a device for compensating the input offset voltage of an amplifier.
FIG. 1 very schematically shows an amplifier structure. This amplifier comprises a differential input stage 10 powered between a high potential Vcc and a low potential Vss. This stage can comprise multiple elementary gain stages comprised of transistors assembled as differential amplifiers. Stage 10 comprises a differential output comprised of two legs D+ and D- respectively carrying a direct current and a current of opposite phase, both proportional to the voltage present between two input terminals E+ and E- of stage 10. These currents in legs D+ and D- are added to a bias current Id. Legs D- and D+ are respectively connected to the input and to the output of a current mirror M1 coupled to the low potential Vss. Leg D+ is also connected to the input of an output stage 11 comprising a control stage 12 controlling, for example, via an output N and an output P the respective bases of "push-pull" connected transistors Q and QP.
FIG. 2 shows an exemplary constitution of a current mirror depending on the low potential Vss, which can be used for mirror M1 and for mirrors which will be described later. This mirror comprises two NPN transistors QMA and QMB, the emitters of which are connected to the low potential Vss, and the bases of which are connected to each other. The collector and the base of transistor QMB are connected to the emitter of a transistor QMC, the base of which is connected to the collector of transistor QMA. The input of the mirror corresponds to the collector of transistor QMA and the output to the collector of transistor QMC. The output current of such a mirror is substantially equal to the input current multiplied by the surface ratio of transistors QMB and QMA.
In the output stage 11 of FIG. 1, a current source IP connected to the high potential Vcc and a current source I.sub.N connected to the low potential Vss establish the bias currents of transistors of the control stage 12. A detailed exemplary schematic diagram of stage 12 providing a follower stage will be described later.
With this configuration, a current equal to the difference between the current in leg D+ and the current in leg D- is provided to the input of the control stage 12. If stage 12 is perfect, a same bias current Id is present in both legs D+ and D-, the current consumed by stage 12 from leg D+ being zero.
However, stage 12 always pushes (as shown) or pulls a parasitic current I.sub.O in leg D+. This parasitic current causes a bias current offset in legs D+ and D- which results in an input offset voltage V.sub.O which must be applied between terminals E+ and E- for compensating the current offset. This offset voltage V.sub.O is particularly great in fast amplifiers which comprise an input stage 10 with only one gain stage. Moreover, in fast amplifiers, the output stage has a high bias current and tends to therefore push a high parasitic current in leg D+.
In order to compensate for this disadvantage in conventional fast operational amplifiers, one of the bias currents of control stage 12, generally current I.sub.N, is adjusted after the manufacturing of the chip of the operational amplifier. This adjustment is generally achieved by laser trimming a resistor. This operation substantially increases the cost of the chip.
FIG. 3 shows in detail a conventional configuration of control stage 12 that provides a follower stage. The input of stage 12 corresponds to the bases of an NPN transistor QD.sub.1 and of a PNP transistor QDP.sub.1 connected in common collector configuration. Current sources IP and I.sub.N are respectively connected to the emitters of transistors QDP.sub.1 and QD.sub.1, and establish the bias current of these transistors. The emitters of transistors QDP.sub.1 and QD.sub.1 respectively correspond to the outputs N and P of control stage 12. With this configuration, transistor QDP.sub.1 and QD.sub.1 consume base currents of respectively Ip/.beta.p and I.sub.N /.beta..sub.N, where .beta.p and .beta..sub.N designate the respective gains of transistors QDP.sub.1 and QD.sub.1. Thus, parasitic current I.sub.0 is equal to: EQU I.sub.0 =IP/.beta..sub.P -I.sub.N /.beta..sub.N.
In general, on the same chip, the gains of the PNP transistors are independent of and lower than the gains of the NPN transistors. The values of currents I.sub.P and I.sub.N are selected in order to cancel the parasitic current I.sub.0 for typical values of gains .beta..sub.P and .beta..sub.N. However, in most cases where these gains are different from their typical values, a parasitic current I.sub.0 subsists. As previously mentioned, an expensive solution includes trimming the value of one of the currents I.sub.P and I.sub.N after manufacturing the chip.
FIG. 4 shows a solution used in conventional non-fast operational amplifiers (with more than one gain stage). As in FIG. 1, output legs D- and D+ of an input stage are connected to a current mirror M1. An output stage 11 pushes a parasitic current I.sub.0 in leg D+. Leg D- is connected to a fake stage 24 which has the same input characteristics as stage 11, i.e. it pushes a current I.sub.0 in leg D-.
With this configuration, legs D- and D+ are balanced and the input offset voltage of the amplifier is compensated.
However, fake stage 24, in order to have the same characteristics as stage 11, must comprise transistors having the same bias current as that of the corresponding transistors of stage 11. If this assembly is used in a fast operational amplifier, the power consumption of the amplifier is increased by approximately 40% for an amplifier already consuming a high current (for example about 20 mA). For this reason, fast operational amplifiers having a fake stage are not manufactured.